1. Field of the Invention
The invention concerns a programmable logic array (PLA) and, in particular, the testing and loading of a PLA made up of an AND array and an OR array and in which the cross points in the arrays are controlled by storage flip-flop circuits.
Signals corresponding to a number of binary variables are applied to the input of such a PLA, and, depending upon the programmed activation of the cross points in the two arrays, output signals are received on particular output lines (function lines). A preferred application of such a PLA may be its use as a function control in a data processing system. For this purpose, the binary operation signals of an instruction are applied to the input of the PLA, and the data flow is controlled by means of the output signals on particular function lines.
Large-scale integration (LSI) permits relatively large PLAs together with the storage flip-flop circuits to be realized on one chip. As a result, the output lines of the AND array, which simultaneously form the input lines to the OR array and which are referred to as "product lines", are no longer accessible from the outside. This makes the testing of a PLA far more difficult. Such testing may be effected during or after completion of manufacture or during the operation of the PLA in a data processing system. In such a test, the object is to determine whether a line or a transistor at the cross point of a matrix has become stuck at a single logic level.
A line may be, for example, short-circuited to ground or to the supply voltage. The line may be interrupted, and in most cases an interrupted line assumes one of these potentials. If the nodes of the arrays, i.e., the means existing at a cross point, comprise a tranistor connected to one or both lines of the cross point, such a transistor may be either interrupted or short-circuited in the case of a fault, thus causing the line connected to it to assume one of the two supply potentials.
Apart from a few exceptions, it is not possible to test a PLA during its operations in a data processing system. So far, testing has been effected before installation of the PLA in the data processing system by applying special test signals and comparing the output signals with known desired values or testing after installation has been made by interrupting the normal operation and then using a diagnostic routine which also applies test patterns to the input of the PLA.
2. The Prior Art
With regard to prior art, attention is drawn, for example, to U.S. Pat. No. 3,958,110 of Se J. Hong and Daniel L. Ostapko and to their theoretical treatise in "Conference on Fault-Tolerant Computing", FTCS-8, Toulouse, June 21 to 23, 1978, pp. 83 to 89. These known arrangements permit testing the PLA only when normal operation has been interrupted. Apart from this, these known methods are not suitable for a PLA with storage flip-flop circuits in the cross points, as they do not utilize the possibility of dynamic personalization characteristic of such a PLA. The complete testing of the PLA rather requires the application of a very great number of test signal combinations and thus a long test period.
U.S. Pat. No. 3,987,286 of Eugen I. Muehldorf teaches a logic arrangement consisting of two series-connected arrays. The cross points of one of the arrays may be personalized by loadable flip-flop circuits, while the array matrix is permanently personalized. For testing, all flip-flop circuits of an array may be connected in the form of a single shift register, through which a test pattern is shifted.
A PLA with transistors at the cross points is described in the IBM Technical Disclosure Bulletin, July 1976, pp. 588 to 590. The base of each of the transistors is connected to the input line, and the emitter of each of the transistors is connected to the output line (referred to as word line). For each word line there is a further transistor which becomes conductive when a cross point transistor connected to the word line is short-circuited between its base and emitter or emitter and collector. This arrangement permits error correction insofar as further dummy lines are provided for the word lines and a further dummy output line is provided for the output lines of the OR array. In these output lines, a random binary pattern may be stored, as the cross point between the dummy line and the PLA line connected thereto is controlled by one storage element. The storage elements in the dummy lines are combined in the form of a shift register. Thus, this known arrangement only permits detecting very specific errors, i.e., whether a transistor has become struck in its conductive state. As the cross points in the arrays of this PLA, which realize the desired binary functions, are not provided with storage elements, this arrangement cannot utilize the advantages of dynamically personalizing a PLA with storage elements at the cross points. Therefore, this known arrangement is not suitable for systematically and completely testing the PLA. Lipp, "Array Logic" in "Second Euromicro Symposium on Microprocessing and Microprogramming", Oct. 12 to 14, 1976, Venice, pp. 57 to 64, proposes in FIG. 2 the use of storage elements for controlling a cross point in a PLA.